120 lines
2.8 KiB
ArmAsm
120 lines
2.8 KiB
ArmAsm
# Copyright (c) (2011-2016,2018-2020) Apple Inc. All rights reserved.
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#
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# corecrypto is licensed under Apple Inc.’s Internal Use License Agreement (which
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# is contained in the License.txt file distributed with corecrypto) and only to
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# people who accept that license. IMPORTANT: Any license rights granted to you by
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# Apple Inc. (if any) are limited to internal use within your organization only on
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# devices and computers you own or control, for the sole purpose of verifying the
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# security characteristics and correct functioning of the Apple Software. You may
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# not, directly or indirectly, redistribute the Apple Software or any portions thereof.
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#if defined(__arm64__)
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#include "arm64_isa_compatibility.h"
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#include "ccarm_pac_bti_macros.h"
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#define key x0
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#define nblocks w1
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#define in x2
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#define out x3
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#define keylen x4
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#define t x5
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.subsections_via_symbols
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.text
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.p2align 4
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.globl _AccelerateCrypto_ecb_AES_encrypt
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_AccelerateCrypto_ecb_AES_encrypt:
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BRANCH_TARGET_CALL
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#if BUILDKERNEL
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// save used vector registers
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sub x4, sp, #6*16
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sub sp, sp, #6*16
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st1.4s {v0,v1,v2,v3}, [x4], #4*16
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st1.4s {v4,v5}, [x4], #2*16
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#endif
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ldr w4, [key, #240] // keylength = 32-bit, 160/192/224
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subs nblocks, nblocks, #4 // pre-decrement nblocks by 4
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ldr q5, [key, keylen] // expanded key
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b.lt 1f // if nblocks < 4, go to scalar loop
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L_4blocks:
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// handle 4 blocks per iteration
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ldr q4, [key] // expanded key
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mov t, #16
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ld1.4s {v0,v1,v2,v3}, [in], #4*16
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0:
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AESE 0, 4
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AESMC 0, 0
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AESE 1, 4
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AESMC 1, 1
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AESE 2, 4
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AESMC 2, 2
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AESE 3, 4
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AESMC 3, 3
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ldr q4, [key, t] // expanded key
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add t, t, #16
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cmp t, keylen
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b.lt 0b
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AESE 0, 4
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eor.16b v0, v0, v5
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AESE 1, 4
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eor.16b v1, v1, v5
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AESE 2, 4
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eor.16b v2, v2, v5
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AESE 3, 4
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eor.16b v3, v3, v5
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st1.4s {v0,v1,v2,v3}, [out], #4*16
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subs nblocks, nblocks, #4
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b.ge L_4blocks
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1: // handle 1 block per iteration
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ands nblocks, nblocks, #3
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b.eq 9f
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L_1block:
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ldr q4, [key] // expanded key
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mov t, #16
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ldr q0, [in], #16 // plain data
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0:
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AESE 0, 4
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AESMC 0, 0
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ldr q4, [key, t] // expanded key
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add t, t, #16
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cmp t, keylen
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b.lt 0b
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AESE 0, 4
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eor.16b v0, v0, v5
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str q0, [out], #16
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subs nblocks, nblocks, #1
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b.gt L_1block
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9:
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#if BUILDKERNEL
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// restore used vector registers
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ld1.4s {v0,v1,v2,v3}, [sp], #4*16
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ld1.4s {v4,v5}, [sp], #2*16
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#endif
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mov x0, #0
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ret lr
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#undef in
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#undef out
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#undef key
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#undef nblocks
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#undef keylen
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#endif
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